As a switching element (a power semiconductor device) configured to perform a large current switching operation, a power MOSFET, an insulated gate bipolar transistor (IGBT) and the like are used. Regarding the switching element, a trench gate type in which an insulation film and a gate electrode are formed in a recess (trench) formed in a semiconductor substrate is used. In the IGBT, a width of the recess is typically set to about 1 μm or smaller (for example, refer to 2013-524481A).
FIG. 5 is a sectional view illustrating an example of a configuration of a trench gate-type semiconductor device 110. In FIG. 5, an n−-type layer 182 and a p−-type layer 183 are sequentially formed on an n+-type layer 181 to be a drain layer in a semiconductor substrate 180. Recesses 185 penetrating the p−-type layer 183 are formed on a front-side of the semiconductor substrate 180. The plurality of recesses 185 (four recesses in a shown range) are formed in parallel to extend in a direction perpendicular to a sheet of FIG. 5. An oxide film 186 is uniformly formed on an inner surface of each recess 185 and a gate electrode 187 is formed to fill in the recess 185.
Also, an n+-type layer 188 to be a source region is formed at both sides of the recess 185 on the front-side of the semiconductor substrate 180. A source electrode 189 is formed on the surface of the semiconductor substrate 180. On the other hand, a whole back-side of the semiconductor substrate 180 is formed with a drain electrode 190 with being contacted to the n+-type layer 181. In the meantime, since an interlayer insulation film 191 is formed to cover the recess 185 on the front-side of the semiconductor substrate 180, the source electrode 189 is contacted to both the n+-type layer 188 and the p−-type layer 183 and is insulated from the gate electrode 187. On the front-side beyond the range shown in FIG. 5, all the gate electrodes 187 are connected to a common gate wiring at end portion-sides of the recesses 185 in the extension direction (the direction perpendicular to the sheet). Also, in the range shown in FIG. 5, the source electrode 189 is formed on the entire surface. However, the gate wiring and the source electrode 189 are separated on the front-side. For this reason, for each recess 185, the p−-type layer 183 at the sides of the recess 185 is formed with a channel by a voltage applied to the gate wiring (the gate electrode 187), so that the semiconductor device 110 becomes an on-state. That is, it is possible to switch the current between the source electrode 189 and the drain electrode 190 by the voltage applied to the gate electrode 187. Since the channels formed for each recess 185 are connected in parallel, it is possible to supply a large current between the source electrode 189 and the drain electrode 190.
In the meantime, although FIG. 5 illustrates a structure of the power MOSFET, the same structure can be applied to an IGBT. In this case, a structure where a p-type layer (a collector layer) is arranged at a lower layer of the semiconductor substrate 180 and a back-side electrode is contacted to the collector layer may be possible, for example. That is, the back-side electrode functions as a collector electrode.
In order to operate the semiconductor device at high speed, it is necessary to make a feedback capacity Crss and an input capacity Ciss small. In the structure of FIG. 5, the feedback capacity Crss is a capacity between the gate electrode 187 and the drain electrode 190 and the input capacity Ciss is a sum of a capacity between the gate electrode 187 and the source electrode 189 and the feedback capacity Crss. Here, in the structure of FIG. 5, since there is a capacity resulting from the oxide film 186 interposed on a bottom part of the recess 185, it is difficult to make the feedback capacity Crss small. It is obvious that when the oxide film 186 is thickened, the feedback capacity Crss can be made to be small. However, since the other characteristics of the semiconductor device as well as the operating speed also depend on the thickness of the oxide film 186, the thickness of the oxide film 186 is normally set so that a desired characteristic except for the operating speed is obtained. Therefore, contrary to the interlayer insulation film 191, the oxide film 186 is formed to be thin by a thermal oxidation causing an interface characteristic with the semiconductor layers (the p−-type layer 183 and the like) to be particularly favorable. In this case, it is difficult to reduce the feedback capacity Crss.
In order to solve the above problems, a structure where the oxide film 186 is particularly thickened only on the bottom part of the recess 185 is considered. Also, a configuration is considered in which the recess 185 is provided on its bottom part with a first semiconductor layer and a first oxide film having the same configuration as the gate electrode 187 and the oxide film 186, respectively, and the gate electrode 187 and the oxide film 186 are formed thereon.
According to the above structures, it is possible to make the feedback capacity Crss small. Meanwhile, in the structures, the oxide film 186 on the p−-type layer 183 (the side surface) at the side surface of the recess 185 at which the channel is formed is formed to be thin. Thereby, it is possible to obtain the semiconductor device having the favorable characteristics, in addition to the operating speed.